This disclosure relates to non-volatile storage.
Semiconductor memory has become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. With flash memory, also a type of EEPROM, the contents of the whole memory array, or of a portion of the memory, can be erased in one step, in contrast to the traditional, full-featured EEPROM.
Both traditional EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage (VTH) of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory element can be programmed/erased between two states, e.g., an erased state and a programmed state. Such a flash memory device is sometimes referred to as a binary flash memory device because each memory element can store one bit of data.
A multi-state (also called multi-level) flash memory device is implemented by identifying multiple distinct allowed/valid programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits encoded in the memory device. For example, each memory element can store two bits of data when the element can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges.
Typically, a program voltage VPGM applied to the control gate during a program operation is applied as a series of pulses that increase in magnitude over time. In one possible approach, the magnitude of the pulses is increased with each successive pulse by a predetermined step size, e.g., 0.2-0.4 V. VPGM can be applied to the control gates of flash memory elements. In the periods between the program pulses, verify operations are carried out. That is, the programming level of each element of a group of elements being programmed in parallel is read between successive programming pulses to determine whether it is equal to or greater than a verify level to which the element is being programmed. For arrays of multi-state flash memory elements, a verification step may be performed for each state of an element to determine whether the element has reached its data-associated verify level. For example, a multi-state memory element capable of storing data in four states may need to perform verify operations for three compare points.
A significant problem with storing multiple bits per cell is that the programming and reading performance may become significantly slower, if reasonable Flash memory reliability (e.g., cycling and data retention specification) is to be achieved. A reason for the reduced performance is that in order to obtain reasonable memory reliability, narrow cell voltage distributions (CVDs) need to be achieved. This requires performing a very controlled programming procedure by using small programming steps and verifying which cells have reached their intended state after each programming pulse. Thus, the increased number of programming pulses and the increased number of states that needs to be verified after each pulse significantly decrease the programming speed.
U.S. Pat. No. 7,073,103, entitled “Smart Verify For Multi-State Memories,” incorporated herein by reference in its entirety, describes a process for minimizing the number of sequential verify operations for each program/verify/lockout step of a write sequence. Initially, only the lowest state of the multi-state range to which selected storage elements are programmed is checked during the verify phase. Once the first storage state is reached by one or more of the selected elements, the next state in a sequence of multi-states is added to the verify process. This next state can either be added immediately upon the fastest elements reaching the preceding state in the sequence, or after a delay of several program pulses. The adding of states to the set being checked in the verify phase continues through the rest of the set of multi-states in sequence, until the highest state has been added. Additionally, lower states can be removed from the verify set as all of the selected storage elements bound for these levels verify successfully to those target values and are locked out from further programming. Note that this technique may require that more than one state be verified following each programming pulse.
However, further improvements are desired.